1. Field of the Invention
The present invention generally relates to high performance semiconductor integrated circuit devices and, more particularly, to passive heat transfer structures therein, especially integrated circuits formed on silicon-on-insulator substrates.
2. Description of the Prior Art
Recent advances in integration density of integrated circuit devices have resulted in decreased signal propagation times and shorter operation cycle times in integrated circuits as well as improved noise immunity and economy of manufacture. However, increased switching rates and integration density engender greater power dissipation per unit area of an integrated circuit chip. As is well-recognized in the art, power dissipation is increased during the short but finite turn-on and turn-off times of both bipolar and field effect transistors. Additionally, peripheral circuits, electrostatic discharge (ESD) circuits (which develop large currents from the discharge) such as off-chip drivers and clocks (which must accommodate large fan-out) require good thermal transport to avoid thermal failure.
In an effort to obtain improved transistor performance through reduced source/drain capacitance allowing higher switching speed or lower voltage operation or a combination of the two, silicon-on-insulator (SOI) wafers/substrates have recently become a technology of choice for many types of devices such as processors, analog circuits and dynamic memories. Such substrates generally include a so-called xe2x80x9chandling substratexe2x80x9d of bulk silicon to provide a sufficient degree of mechanical robustness to withstand processing and packaging of integrated circuits.
The composition of the handling substrate is of reduced importance since it is covered with a relatively thick layer of insulator (generally an oxide on the substrate material) and another layer of high purity silicon (hereinafter referred to as the xe2x80x9cactive layerxe2x80x9d) on and/or in which the active devices of the integrated circuit are formed. Although the electrical properties of the handling substrate are substantially unimportant since the active device structures are generally separated therefrom by the thick insulator layer, the thermal properties are important for SOI devices, particularly for the types of circuits for which they are most advantageously employed.
However, the thick insulator layer is a relatively poor conductor of heat compared to the high thermal conductivity of silicon and metals and presents a substantial thermal barrier to heat transfer to the handling substrate. Likewise, the active devices are covered with a number of layers of insulator and a passivation layer of insulator which also presents a barrier to heat transfer. Therefore, power dissipation is substantially limited to paths to the surface of the integrated circuit through conductive vias which form contacts to the active regions formed in the silicon layer on the insulator. These heat conduction paths (only slightly supplemented by heat transfer through the insulators to the front and back sides of the chip) have been found insufficient to maintain adequately low temperatures of SOI integrated circuits having high performance SOI devices integrated at high density thereon.
A partial solution to improving heat dissipation from SOI chips is disclosed in U.S. patent application Ser. No. 09/514,106, filed concurrently herewith, now U.S. Pat. No. 6,288,426, assigned to the assignee of the present invention and hereby fully incorporated by reference. As disclosed therein, a thermal poly plug (TPP), insulated from the silicon of the active layer and the handling substrate by a thin insulator, is formed through the thick insulator layer of the SOI structure. The thin insulator and substantial peripheral area of a TPP provides a path of low thermal resistance between the silicon active layer and the silicon handling substrate. A plurality of TPPs can be distributed as desired throughout a chip design to regulate temperature variation across the chip. An area comparable to that required for one to three transistors is adequate to provide a substantial thermal path equivalent to several hundred times that area through the thermal barrier of the thick insulator.
Thus the back side of the chip also is provided for dissipation of heat although the amount of heat conducted through an array of TPPs may be limited by the area required for their formation and which is thus unavailable for the formation of active devices of the integrated circuit. Further, the back side of the chip is usually used to support the chip in a lead frame or other portion of the packaging structure and the amount of heat that can be dissipated therefrom is usually somewhat limited as well. Therefore, while TPP structures may greatly increase the heat dissipation properties of a chip, there is no assurance that the heat dissipation will be adequate to the integrated circuit design. No technique of further increasing heat transfer from the active layer of a SOI integrated circuit has heretofore been proposed, other than increasing the number of TPPs included in the chip design with consequent reduction in density of active devices and loss of functionality and performance.
It is therefore an object of the present invention to provide an additional heat transfer enhancement for integrated circuit chip and SOI chips, in particular.
It is another object of the invention to provide a heat transfer structure which is compatible with passive heat sinks and active cooling devices.
In order to accomplish these and other objects of the invention, a method of fabricating a semiconductor device having increased heat dissipation properties is provided including the steps of forming a recess in a substrate, filling the recess with a thermally conductive material to form a plug, forming active devices at a surface of the substrate adjacent the plug, applying an insulator layer over the active devices and the plug, and forming a thermally conductive path from the plug through the insulator layer to a surface of the insulator layer.
In accordance with another aspect of the invention, a semiconductor device is provided comprising a substrate having a thermal barrier below an active device region, an insulator layer overlying the active device region, a thermally conductive plug insulated from the active device region and extending through the thermal barrier, and a thermal conductor structure extending from the thermally conductive plug through the insulator layer overlying the active device region. Additional thermal conductor structures may be added to extend through other insulator layers to heat sinks.